The present invention relates to a rhythm generator which is simplified in construction by reducing the number of envelope coefficient memories for loading envelope information.
Heretofore, there have already been made several proposals for improvement of a rhythm generating circuit of the type employing a tone source summing coefficient and an attack/decay coefficient for generating a plurality of tone sources. This type of rhythm generating circuit comprises a tone source unit for generating a tone source frequency by selection of a rhythm and an envelope unit for imparting an envelope waveshape to the tone source signal. The tone source summing coefficient and the attack/decay coefficient are prestored in memories and various tone source waveshapes or envelope waveshapes are produced by accumulators for the respective coefficients and multiplied in a predetermined combination to generate a desired rhythm note.
FIG. 1 shows the arrangement of a prior example of the rhythm generating circuit. In this case, if the number of tone sources is 16, then 16 channels are needed. The envelope waveshape and the tone source waveshape are formed on a time-divided basis to produce a rhythm note corresponding to a selected rhythm pattern signal. In FIG. 1 a rhythm pattern signal (hereinafter referred to as an attack signal) A is provided to an envelope control circuit 17 to generate timing for attack and decay of the envelope waveshape by signals C1 and C2 described later. A channel specify signal (CH1) from a channel decoder 21, which is specified through an address counter 20 driven by a timing generating circuit 19, is provided to the envelope control circuit 17, from which is applied a specified address signal to an envelope coefficient memory 13 via an OR circuit 15. From the envelope coefficient memory 13 is read out an attack and decay summing coefficient based on an address from the address counter 20 and the summing coefficient thus read out is provided to an accumulator 11 via a coefficient gate 26 controlled to be in the ON state. The accumulator 11 is composed of an adder, a gate circuit, a register and a memory (RAM). Next, an attack signal B is applied to another envelope circuit 18 to generate timing for attack and decay of the envelope waveshape by the signals C1 and C2 as in the case of the envelope control circuit 17. A channel specify signal (CH16) from the channel decoder 21 is provided to the envelope control circuit 18, from which a specified address signal is applied via the OR circuit 15 to the envelope coefficient memory 13. In this case, when the attack end signal C1 is generated from the accumulator 11, a control signal from the envelope control circuit 18 becomes high-level, by which the coefficient gate 26 is altered to the OFF state, cutting off the coefficient from the envelope coefficient memory 13 to the accumulator 11. As a result of this, the accumulator 11 adds "0", and hence it continues to hold and output the same value. In other words, the operations of the envelope control circuits 17 and 18 differ in the ON-OFF state of the coefficient gate 26 at the time of generation of the attack end signal C1 from the accumulator 11, by which an envelope with no hold state or an envelope with a hold state is selected. In this circuit these two kinds of waveshapes are contained in a specified channel.
The accumulator 11 accumulates the summing coefficients specified by the addresses from the address counter 20 and channel specify signals fed from the envelope control circuits 17 and 18 via an OR circuit 16 and yields eight-bit binary address information as an accumulated output signal, which is provided to an envelope waveshape table 14. The data to be processed by the accumulator 11 is 10-bit and includes carry signals C1 and C2 in addition to the abovesaid eight-bit address data. In the case where the eight-bit address data is provided to the envelope waveshape table 14, only five high-order bits are used for an address, discarding the remaining three low-order bits. The signal C1 indicates the end of the attack period and the signal C2 indicates the end of decay. The both signals are applied to the envelope control circuit 17. The accumulator 11 provides an accumulated output signal of 16 envelope waves corresponding to 16 channels.
Next, the content of the envelope waveshape table 14 is applied to an exclusive OR circuit 22. When the signal C1 assumes a higher level than does the initial value of the next cycle after completion of 32 words of an attack waveshape by the signal C1, the data from the envelope waveshape table 14 is inverted to form a decay waveshape. The output from the exclusive OR circuit 22 is converted by a D-A converter 23 to analog form, obtaining an envelope waveshape.
A tone source unit is similar in construction to the envelope unit. In synchronism with a channel address from the address counter 20, a tone source summing coefficient is read out from a tone coefficient memory 30 and applied to a tone accumulator 31 composed of an adder, a gate circuit, a register and a memory (RAM). In the tone accumulator 31 tone coefficients are accumulated to provide an accumulated output signal corresponding to a tone source frequency, which is applied as an address to a 256-word sine wave table 32 to output therefrom a sine wave of half-wavelength. This output is provided to an exclusive OR circuit 33 as in the case of the envelope and inverted by a carry signal C1' of the accumulated output signal from the tone accumulator 31 to obtain a digital sine-wave tone source waveshape. The frequency of this tone source waveshape is applied to a multiplying type D-A converter 34, wherein it is converted into an analog signal multiplied by the envelope waveshape available from the D-A converter 23 which forms a part of the aforementioned envelope unit. And the analog data time-divided by an analog multiplexer 35 of the next stage is distributed to the channels CH1 to CH16 and analog data of 1/16 unit time is held by a sample hold circuit 36, thereafter being outputted.
One method that the present inventor has proposed for simplifying the arrangement described above is to accumulate the frequency information and the envelope information by use of a common accumulator on a time-divided basis, as shown in an embodiment described later. Further, although in the prior structure the envelope coefficient memory stores the attack and decay coefficients at different addresses, the present inventor has proposed to switch the coefficients outside of the envelope coefficient memory to reduce its capacity by half, taking notice of the fact that both the coefficients can be loaded at the same address.